Many devices such as synchronous dynamic random access memory (SDRAM) and microprocessors receive an external clock signal generated by an external clock source such as a crystal oscillator. The external clock signal received through an input pad on the device is routed to various circuits within the device through a tree of buffer circuits. The buffer tree introduces a common delay between the external clock and each buffered clock.
Typically, a delay locked loop (DLL) with an adjustable delay line is used to synchronize the buffered clock signal with the external clock signal by delaying the external clock signal applied to the buffer tree. The DLL includes a phase detector, which detects the phase difference between the external clock signal and a buffered clock signal. Based on the detected phase difference, the DLL synchronizes the buffered clock signal to the external clock signal by adding an appropriate delay to the external clock signal until the buffered external clock signal (the internal clock) is in phase with the external clock signal. The DLL can be implemented as an analog delay locked loop or a digital delay locked loop. In an analog delay locked loop, a voltage controlled delay line is used to delay the external clock signal.
FIG. 1 is a block diagram of a prior art analog delay locked loop (DLL) 100. The analog DLL 100 synchronizes an internal clock signal CKI with an external clock signal CKE. The external clock CKE signal is coupled to a voltage controlled delay line 102, and the voltage controlled delay line 102 is coupled to clock tree buffers 108. The delayed external clock signal CKE is fed into the clock tree buffers 108 where it propagates to the outputs of the tree and is applied to the various circuits. The delay through the clock tree buffer 108 results in a phase difference between the external clock signal CKE and the internal clock signal CKI. The voltage controlled delay line 102 adjusts the delay of the external clock signal CKE by either increasing or decreasing the delay, to synchronize the external and internal clock signals.
To determine the appropriate delay in the delay line, one of the outputs of the clock tree buffers 108 is coupled to a phase detector 104 where it is compared with the external clock signal CKE. The phase detector 104 detects the phase difference between the internal clock CKI and the external clock CKE. The output of the phase detector 104 is integrated by a charge pump 106 and a loop filter capacitor 112 to provide a variable bias voltage VCTRL 110 for the voltage controlled delay line (VCDL) 102. The bias voltage VCTRL selects the amount of delay to be added to the external clock signal by the VCDL 102 to synchronize the internal clock signal CKI with the external clock signal CKE.
The phase detector 104 is a D-type flip-flop with the D-input coupled to the external clock signal CKE and the clock input coupled to the internal clock signal CKI. On each rising edge of the internal clock signal CKI, the output of the phase detector 104 indicates whether the rising edge of the internal clock signal is before or after the rising edge of the external clock signal.
The analog DLL 100 produces a voltage controlled delay with high accuracy. However, performance of the analog DLL varies over a frequency range because the delay generated using the voltage controlled delay line varies non-linearly with changes in the bias control voltage VCTRL.
FIG. 2 is a graph illustrating the non-linear control voltage characteristic for the voltage controlled delay line shown in FIG. 1. In general, devices support a wide range of external clock frequencies within which an operational frequency is selected for a particular device. In the example shown in FIG. 2, the device can operate at any frequency between point A and point C. The operational frequency selected is at point B.
As shown, the control voltage characteristic is non-linear: sharp at one end of the control voltage range (point C) and almost flat at the opposite end (point A). This control voltage characteristic results in DLL instability at point C and long lock times at point A. The wide range of frequencies (delays) is controlled by the bias voltage VCTRL.
Referring again to FIG. 1, the bias voltage VCTRL is the output of the charge pump 106, which remains in a high-impedance state most of the time. Any noise on the bias voltage signal VCTRL disturbs the output of the analog DLL 100. For example, if the analog DLL is operating at point B, a small voltage change (ΔV) due to noise results in a large change in delay. Thus, the analog DLL is very sensitive to noise when operating at point B, within the wide frequency range shown from point C to point A. Therefore, the analog DLL is not stable within a wide frequency range.
A digital DLL does not have the stability problem of an analog DLL. However, the accuracy of a digital DLL is as high as the accuracy of an analog DLL, because the delay is provided by combining fixed quantum (steps) of delay. The smaller the step of delay, the higher the accuracy. However, a decrease in step size results in a corresponding increase in silicon area because more delay elements are required to cover the wide frequency range.